News Steven LevitanJohn A. Jurenko Professor, Department of Electrical and Computer Engineering
In his first Smithies lecture, Levitan discussed the two drivers for current research in the field of design automation for electronic systems: the problems that stem from the complexity of our large designs and the problems that come from the uncertainty in the behavior of our smallest devices. At the “Giga” level, design complexity challenges us both as human designers needing to work with large teams and in design tools, which often have significant run-time complexity, being applied to problem sizes in the billions (109). At the “Nano” level, problems of design for manufacturing and design for yield are exacerbated by the “tyranny of small numbers”. Variations of a few atomic layers in the gate oxide thickness of the transistors, or a few nanometers in their channel length are large fractions of their critical dimensions, and therefore cause large variations in their behaviors. In the second lecture, he reviewed the well known paradigms for parallel computer architectures and algorithms and presented his view on the methods that have the most promise of success in the emerging set of new “multi-core” computer chips from IBM, Intel, and ARM. In the 1970’s and 1980’s the promise of parallel processing was expected to be realized with the advent of very large scale integration (VLSI); however, rather than the development of commodity parallel processors, industry turned its energy to making faster and more powerful uni-processors. Now, new problems (most notably power) are forcing us to re-examine parallel architectures and the programming paradigms that can become accessible to mainstream applications. These two topics have been recurring and interwoven themes in Levitan’s research career. His early work focused on the relationship of parallel algorithms to the parallel computer architectures that were designed to support them where he determined that commonly accepted metrics for the interconnection graphs of parallel processors were not the best predictors for parallel algorithm performance. Rather, the performance of “kernel” tasks, which are composed to create useful applications, are themselves better predictors of the performance of these applications. This work led to the development of better hardware structures for parallel computer architectures, and in particular optoelectronic circuits and systems. The fundamental advantages of optics as a communications medium for information processing is not in the “speed of light,” but rather the unique qualities of light in its non-interference, low temporal dispersion, and information capacity. Together with Professor Donald Chiarulli in Computer Science, he developed several unique optoelectronic networks including the partitioned optical passive star (POPS) network, optical address busses, optoelectronic routers, and the use of predictive control for time multiplexed optical circuit switched networks. Unfortunately, software design tools for such systems are severely lacking and the ability to design and predict the performance of a computing system that uses non-electronic components is severely hampered by this lack of modeling and simulation tools. Therefore, Steve and Don have investigated the modeling and simulation of mixed-technology systems spanning not only electronics and optics, but also encompassing mechanical design. This work culminated in a design framework named “Chatoyant,” which is a mixed-signal multi-level simulation backbone for these multi-technology systems. Chatoyant has been used to design and analyze many opto-electronic and mechanical-opto-electrical microsystems (MOEMS) built by the group, as well as industry and government funded projects. The modeling tools developed by our group are not only applicable to macro-scale devices, but can also be applied to micro and emerging nano-scale components. It is at this level that there has been a re-emergence of interest in parallel computing. The promise of billions of computing devices working together to solve a common problem has led many to rethink the paradigms for parallel processing that were shelved in the 1990’s in favor of highly optimized single processor computers. At Pitt, Steven Levitan is the John A. Jurenko Professor in the Department of Electrical and Computer Engineering. He chaired the 2007 Design Automation Conference, which was attended by 10,000 people and featured more than 50 technical sessions as well as an exhibition with more than 250 participating companies. Levitan’s accomplishments do not stop there. Please visit his Web site for more about his research and credentials. |
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Steve Levitan has been working this year in England, where he is an Oliver Smithies Lecturer and a visiting fellow of Balliol College at Oxford University. The Oliver Smithies Lectureship is awarded to a visitor to present two university-wide lectures on a subject of the lecturer’s choosing. While a visiting fellow, Levitan has been collaborating with Oxford’s Dominic O’Brien, a reader in electrical engineering, and Thomas Melham, a professor of computer science.Benedum Hall
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